FPGA HDMI Framebuffer Pipeline (720p)

Implemented a complete HDMI video output pipeline on a Xilinx Spartan-7 FPGA, featuring a DDR3-backed framebuffer for smooth video rendering. The design includes custom memory controllers, pixel processing pipelines, and HDMI encoding logic, all achieving clean timing closure at 720p resolution. This project demonstrates advanced digital design skills and understanding of video standards.